Source: Hot Chips The accelerated life cycles that AI is driving woke up a normally sleepy August. Held virtually, Hot Interconnects (HotI 2025) spanned three days with a mix of invited talks, sponsor talks, and tutorials. Some of the brief sponsor talks merely previewed larger disclosures at Hot Chips, which was held at Stanford University the following week. This year, Hot Chips’ agenda included an Optical session that featured three startups plus Nvidia. It also included Networking and Machine Learning (ML) sessions with talks from leading vendors. Although Nvidia was the marquee name in Hot Chips' Optical session, Gilad Shainer's talk on co-packaged silicon photonics lacked any new technical details on the company's CPO switches. Instead, the company used the event to announce Spectrum-XGS, which extends its Spectrum-X Ethernet solution across data centers. Nvidia calls this "scale-across" networking because it primarily targets data center clusters, but it is...

August marked the in-person return of the   Hot Chips   conference at Stanford University in California, and the sold-out 35th edition included plenty of deep technical content. AI/ML garnered lots of attention and optical interconnects were featured in both chip- and system-level AI and HPC talks.   NVIDIA’s   chief scientist, Bill Dally, keynoted Day 2 with a talk reviewing how accelerators achieved a 1,000x performance increase over the last 10 years. His big-picture view provided excellent context for AI-system design, but networking received only an honorable mention this year. Instead, Dally discussed future directions for accelerated compute. Following the keynote, an  ML-Training  session presented talks from Google and Cerebras. The technical lead for TPUs at  Google , Norm Jouppi made it clear he could only discuss the n-1 generation, meaning TPUv4. Meanwhile, Google revealed the TPUv5e at its own Google Cloud Next event the same day but...

I will be at Stanford at the end of this month for the in-person return of Hot Chips . As always, the 35th edition (HC35) will have plenty of deep technical content, with AI/ML unsurprisingly getting lots of attention. I'm particularly interested in a set of talks exploring interconnects and networking for AI, HPC, and beyond. Day 2 (Tuesday, August 29) features an ML-Training session with talks from Google and Cerebras. The technical lead for TPUs at Google , Norm Jouppi will expand on the paper presented at ISCA 2023 describing the TPUv4 supercomputer. That paper revealed Google's use of optical circuit switches in its TPUv4 cluster, following prior disclosures around OCS deployments in its data-center spine layer. Sean Li, cofounder and chief hardware architect at Cerebras , will deliver a talk on the company's cluster architecture built around the CS-2 system and WSE-2 wafer-scale engine. This talk will explore how the MemoryX external-memory system and SwarmX fabric i...