Showing posts from March, 2023

White Paper: The Evolution of Memory Tiering at Scale

With first-generation chips now available, the early hype around CXL is giving way to realistic performance expectations. At the same time, software support for memory tiering is advancing, building on prior work around NUMA and persistent memory. Finally, operators have deployed RDMA to enable storage disaggregation and high-performance workloads. Thanks to these advancements, main-memory disaggregation is now within reach.  Enfabrica sponsored the creation of this white paper, but the opinions and analysis are those of the author. Download the full  white paper  for free, no registration required.

Marvell Teralynx Leapfrogs to 51.2T

About 18 months after acquiring Innovium, Marvell announced its next-generation Teralynx 10 data-center switch chip. The 51.2Tbps design moves the Teralynx architecture to 5nm process technology while also incorporating homegrown 112Gbps PAM4 serdes. It marks the end of the road for the 7nm Teralynx 8 chip, which Innovium sampled but was unable to move to production. Multiple sources confirm that third-party serdes IP was the culprit, and Innovium was only one of several affected customers. The end result for Marvell is that it skipped the 25.6Tbps generation and set its sights on 51.2Tbps. Meanwhile, it has shipped more than 5 million 400GbE ports with the first-generation Teralynx 7, mostly to one hyperscale customer. Teralynx 10 promises an unsurprising feature set, which actually validates Innovium's design approach. The startup found the right balance of programmability and performance, enabling protocol flexibility and P4 in-band networking telemetry (P4-INT). Innovium also t