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Showing posts with the label DPU

BWR Episode 17: Hot Chips 2026

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With so many August events, we chose to focus this BWR episode exclusively on Hot Chips 2026. Joe and Bob discuss key disclosures, including Intel’s Diamond Rapids Xeon, AMD’s Helios MI450 platform, NVIDIA’s LPX/LPU architecture, Cerebras’s CS-4 wafer-scale engine, and OpenAI’s JalapeƱo ASIC. As always, you can find timestamps on YouTube if you want to skip to items of interest.

Introducing The Byrne-Wheeler Report

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My colleague Joe Byrne and I launched a video podcast covering the latest news in the chip world. Episode 1 covers Hot Interconnects and Hot Chips news from August as well as Arm's Lumex announcement and Nvidia's Rubin CPX. We hope you enjoy this new format, which will complement our respective blogs.  

White Paper: Xsight Softens the DPU

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Powering SmartNICs, the data-processing unit (DPU) has become nearly ubiquitous in the leading public clouds. Existing designs maximize power efficiency for a constrained feature set, and they require proprietary software tools. Xsight Labs aims to break this paradigm with its new E1 DPU, which promises the openness of an Arm server CPU. Xsight Labs sponsored the creation of this white paper, but the opinions and analysis are those of the author. Download the white paper for free, no registration required. Xsight E1 DPU