With so many August events, we chose to focus this BWR episode exclusively on Hot Chips 2026. Joe and Bob discuss key disclosures, including Intel’s Diamond Rapids Xeon, AMD’s Helios MI450 platform, NVIDIA’s LPX/LPU architecture, Cerebras’s CS-4 wafer-scale engine, and OpenAI’s Jalapeño ASIC. As always, you can find timestamps on YouTube if you want to skip to items of interest.

Joe and I will be at live events in August. Thanks to LightCounting , I will be at the OCP APAC Summit on August 11-12, moderating panels in the Photonics track and the Chiplets & Advanced Packaging track. Joe will be at Hot Chips at Stanford on August 24-25, and I will be attending virtually. We kick off The Byrne-Wheeler Report with a Hot Chips preview. After that, we review AMD's Advancing AI Day disclosures including GPUs, CPUs, racks, and customer announcements. My audience should be interested in Astera Lab's 3.2T Taurus announcement, which includes something new and different. And with CPUs back in vogue, Joe covers Nvidia's Vera disclosures. You can find timestamps on YouTube if you want to jump to items of interest. As always, thanks for watching!

My colleague Joe Byrne and I launched a video podcast covering the latest news in the chip world. Episode 1 covers Hot Interconnects and Hot Chips news from August as well as Arm's Lumex announcement and Nvidia's Rubin CPX. We hope you enjoy this new format, which will complement our respective blogs.  

Source: Hot Chips The accelerated life cycles that AI is driving woke up a normally sleepy August. Held virtually, Hot Interconnects (HotI 2025) spanned three days with a mix of invited talks, sponsor talks, and tutorials. Some of the brief sponsor talks merely previewed larger disclosures at Hot Chips, which was held at Stanford University the following week. This year, Hot Chips’ agenda included an Optical session that featured three startups plus Nvidia. It also included Networking and Machine Learning (ML) sessions with talks from leading vendors. Although Nvidia was the marquee name in Hot Chips' Optical session, Gilad Shainer's talk on co-packaged silicon photonics lacked any new technical details on the company's CPO switches. Instead, the company used the event to announce Spectrum-XGS, which extends its Spectrum-X Ethernet solution across data centers. Nvidia calls this "scale-across" networking because it primarily targets data center clusters, but it is...

This year's edition of the annual Hot Chips conference represented the peak in the generative-AI hype cycle. Consistent with the theme, OpenAI's Trevor Cai made the bull case for AI compute in his keynote. At a conference known for technical disclosures, however, the presentations from merchant chip vendors were disappointing; despite a great lineup of talks, few new details emerged. Nvidia's Blackwell presentation mostly rehashed previously disclosed information. In a picture-is-worth-a-thousand-words moment, however, one slide included the photo of the GB200 NVL36 rack shown below. GB200 NVL36 rack (Source: Nvidia) Many customers prefer the NVL36 over the power-hungry NVL72 configuration, which requires a massive 120kW per rack. The key difference for our readers is that the NVLink switch trays shown in the middle of the rack have front-panel cages, whereas the "non-scalable" NVLink switch tray used in the NVL72 has only back-panel connectors for the NVLink spin...

August marked the in-person return of the   Hot Chips   conference at Stanford University in California, and the sold-out 35th edition included plenty of deep technical content. AI/ML garnered lots of attention and optical interconnects were featured in both chip- and system-level AI and HPC talks.   NVIDIA’s   chief scientist, Bill Dally, keynoted Day 2 with a talk reviewing how accelerators achieved a 1,000x performance increase over the last 10 years. His big-picture view provided excellent context for AI-system design, but networking received only an honorable mention this year. Instead, Dally discussed future directions for accelerated compute. Following the keynote, an  ML-Training  session presented talks from Google and Cerebras. The technical lead for TPUs at  Google , Norm Jouppi made it clear he could only discuss the n-1 generation, meaning TPUv4. Meanwhile, Google revealed the TPUv5e at its own Google Cloud Next event the same day but...

I will be at Stanford at the end of this month for the in-person return of Hot Chips . As always, the 35th edition (HC35) will have plenty of deep technical content, with AI/ML unsurprisingly getting lots of attention. I'm particularly interested in a set of talks exploring interconnects and networking for AI, HPC, and beyond. Day 2 (Tuesday, August 29) features an ML-Training session with talks from Google and Cerebras. The technical lead for TPUs at Google , Norm Jouppi will expand on the paper presented at ISCA 2023 describing the TPUv4 supercomputer. That paper revealed Google's use of optical circuit switches in its TPUv4 cluster, following prior disclosures around OCS deployments in its data-center spine layer. Sean Li, cofounder and chief hardware architect at Cerebras , will deliver a talk on the company's cluster architecture built around the CS-2 system and WSE-2 wafer-scale engine. This talk will explore how the MemoryX external-memory system and SwarmX fabric i...