At GTC DC last month, Jensen Huang showed off components of the Vera Rubin NVL144 platform. First, here's the latest roadmap, which now includes BlueField-4 and BlueField-5. For more on that, see BWR Episode 4 .  Source: Nvidia Below is the Vera Rubin compute tray, which includes four Rubin GPUs. By GPU, we mean package not die. Note that the Blackwell NVL72 and Rubin NVL144 both have 72 GPU packages, but the NVL144 moniker denotes Nvidia's new math counting die. The company didn't rename the Blackwell configuration, even though that GPU also has two die. Each compute tray has two Vera CPUs, which are 88-core Arm processors. Two GPUs connect with one CPU using NVLink-C2C, a coherent variant of NVLink. Although the roadmap above shows CX9 as 1600G, each ConnectX-9 is actually 800Gbps, requiring eight chips to deliver the aggregate 800GB/s quoted for the tray. That means each GPU has a pair of 800G Ethernet/InfiniBand NICs for scale-out networking. Finally, a single BlueField...

October was a busy month, between the OCP Global Summit and being the lead author on the LightCounting switch report. The new report adds another level of granularity to the scale-up switch forecast, which incorporates NVLink, UALink, Scale-Up Ethernet (SUE), and non-Nvidia proprietary interconnects. There are many other changes to the report, including revisions to the methodology for the co-packaged optics (CPO) forecast. The newsletter summary is freely available: Co-packaged Optics Grow the Scale-out Switch Pie Source: Wheeler's Network

Source: Broadcom Tomahawk Ultra is a misnomer. Although the name leverages Tomahawk's brand equity, Tomahawk Ultra represents a new architecture. In fact, when it began development, Broadcom's competitive target was InfiniBand. During development, however, AI scale-up interconnects emerged as a critical component of performance scaling, particularly for large language models (LLMs). Through luck or foresight, Tomahawk Ultra suddenly had a new and fast-growing target market. Now, the leading competitor was NVIDIA's NVLink. Also happening in parallel, Broadcom built a multi-billion-dollar business in custom AI accelerators for hyperscalers, most notably Google. At the end of April, Broadcom announced its Scale-Up Ethernet (SUE) framework, which it published and contributed to the Open Compute Project (OCP). Appendix A of the framework includes a latency budget, which allocates less than 250ns to the switch. At the time, we saw this as an impossibly low target for existing Eth...

Tomahawk 6 is First to 102.4T Through relentless execution, Broadcom has been first to market generation after generation in data-center switching. The company just announced sampling of Tomahawk 6 (TH6), its 102.4T Ethernet switch ASIC. This generation actually consists of two switch chips, TH6-200G with 512x200G SerDes, and TH6-100G with 1,024x100G SerDes, both of which are sampling now. A version with fully co-packaged optics, TH6-Davisson, will follow on a to-be-announced schedule.  Whereas Tomahawk 5 (TH5) is a monolithic 5nm chip, TH6 comprises a core die and separate chiplets for the two SerDes options, all of which use 3nm technology. Source: Broadcom For AI scale-out networks, TH6 enables a 128K-XPU network using only two switch tiers. Fewer tiers mean lower latency, simpler load balancing and congestion control, and fewer optics. The new chip is first to handle 1.6T Ethernet ports, but it also handles up to 512x200GbE ports for maximum radix. Beyond sheer port density, TH...

In the AI era, silicon-design cycles have become a limiting factor in feature velocity. Network programmability has never been more critical, yet flexibility cannot come at the cost of performance and power efficiency. With its X-Switch architecture, Xsight Labs targeted the sweet spot for data-center switching, balancing performance and power while maximizing programmability. Now, to encourage innovation and adoption, the company opened the instruction sets for its X-Switch programmable Ethernet switch architecture. Xsight Labs sponsored the creation of this white paper, but the opinions and analysis are those of the author. Download the  white paper  for free, no registration required. X-Switch Scalable Architecture

Yes, $11B in Blackwell revenue is impressive. Yes, Nvidia's data-center revenue grew 93% year over year. Under the surface, however, there's trouble in networking. In the January quarter (Q4 FY25), networking revenue declined 9% year over year and 3% sequentially. In its earnings call, CFO Collette Kress said that Nvidia's networking attach rate was "robust" at more than 75%. Her very next sentence, however, hinted at what's happening underneath that supposed robustness. "We are transitioning from small NVLink8 with InfiniBand to large NVLink72 with Spectrum-X," said Kress. About one year ago, Nvidia positioned InfiniBand for "AI factories" and Spectrum-X for multi-tenant clouds. That positioning collapsed when the company revealed xAI selected Spectrum-X for what is clearly an AI factory. InfiniBand appears to be retreating to its legacy HPC market while Ethernet comes to the fore. Nvidia Data-Center Revenue So how do we square 93% DC grow...

Powering SmartNICs, the data-processing unit (DPU) has become nearly ubiquitous in the leading public clouds. Existing designs maximize power efficiency for a constrained feature set, and they require proprietary software tools. Xsight Labs aims to break this paradigm with its new E1 DPU, which promises the openness of an Arm server CPU. Xsight Labs sponsored the creation of this white paper, but the opinions and analysis are those of the author. Download the white paper for free, no registration required. Xsight E1 DPU

Cloud-datacenter operators are driving rapid adoption of 800Gbps optical modules while also upgrading compute-server NICs to 400Gbps speeds. The 51.2Tbps switch chips designed for these network fabrics, however, deliver too much capacity for top-of-rack switch systems. With its X2, Xsight Labs developed a unique chip aimed at optimizing compute racks by enabling 100Gbps-per-lane server links and 800Gbps uplink optics. Xsight Labs sponsored the creation of this white paper, but the opinions and analysis are those of the author. Download the white paper for free, no registration required. Xsight X2

With the formal launch of the MI300 GPU, AMD revealed new plans for scaling the multi-GPU interconnects vital to AI-training performance. The company's approach relies on a partner ecosystem, which stands in stark contrast with NVIDIA's end-to-end solutions. The plans revolve around AMD's proprietary Infinity Fabric and its underlying XGMI interconnect. Infinity Fabric Adopts Switching As with its prior generation, AMD uses XGMI to connect multiple MI300 GPUs in what it calls a hive. The hive shares a homogeneous memory space formed by the HBM attached to each GPU. In current designs, the GPUs connect directly using XGMI in a mesh or ring topology. Each MI300X GPU has up to seven Infinity Fabric links, each with 16 lanes. The 4th-gen Infinity Fabric supports up to 32Gbps per lane, yielding 128GB/s of bidirectional bandwidth per link. At the MI300 launch, Broadcom announced that its next-generation PCI Express (PCIe) switch chip will add support for XGMI. At last October...

Communications-service providers are under pressure to transform their networks for greater bandwidth and efficiency while also enabling new revenue-generating services. In some cases, they have disrupted the traditional supply chain, turning to white-box designs powered by merchant silicon. Broadcom has been at the forefront of this trend with its DNX line of Ethernet chips, better known by the Jericho and Qumran code names. Here, we look at the migration to fixed-configuration systems and how Broadcom’s 5nm Qumran3D chip can serve in the next router generation. Broadcom sponsored the creation of this white paper, but the opinions and analysis are those of the author. Download the white paper for free, no registration required. Qumran3D

Four chip vendors may not sound like a crowd, but in the leading-edge data-center switch segment, it's likely unsustainable over the long term. The problem is the small number of customers for these devices, that is, the hyperscalers. Despite stiff competition, however, Cisco continues to invest in its Silicon One product line, which now includes 5nm switch chips. The new top-end device is the Silicon One G200, a 51.2Tbps chip built around an internally developed 112Gbps serdes. As a refresher, the company announced production of its 7nm 25.6Tbps G100 chip last October along with design wins in new Cisco platforms. As the figure below shows, Cisco makes some bold claims regarding the G200. The most startling is the statement that the G200 is twice as power efficient as its predecessor. In other words, the G200 dissipates the same power as the G100 at twice the throughput. The company's new serdes design must improve power efficiency, as the move from 7nm to 5nm should account f...

This week saw the formal launch of the Ultra Ethernet Consortium (UEC), which aims to reinvent Ethernet fabrics for massive-scale AI and HPC deployments. An impressive list of founding members back this ambitious effort: hyperscalers Meta and Microsoft; chip vendors AMD, Broadcom, and Intel; OEMs Arista, Atos, and HPE; and Cisco, which straddles the chip and OEM camps. Absent this backing, we could easily write off this consortium as doomed to failure. Our skepticism is rooted not in the obvious need the UEC looks to serve but rather in the challenges of standardizing and implementing a full-stack approach. The effort plans to replace existing transport protocols as well as user-space APIs. Specifically, the Ultra Ethernet Transport (UET) protocol will be a new RDMA protocol to replace ROCE, and new APIs will replace the Verbs API from the InfiniBand heritage. UET will provide an alternative to RoCEv2 and Amazon’s SRD , both of which are deployed in hyperscale data centers. (Source: Ul...

There's been a lot of confusion around Spectrum-X, some of which NVIDIA seems to have created intentionally. The company's branding is part of the issue, as it seems to conflate Spectrum-X with the Spectrum line of Ethernet switch chips. In fact, Spectrum-X is simply a software license that enables new features across a set of existing hardware products. The reality that Spectrum-X is a set of software, however, devalues what NVIDIA has actually delivered. Working on top of the company's end-to-end Ethernet hardware, the software creates the first merchant congestion-managed Ethernet fabric. Minimizing tail latency is critical to AI-training workloads, as detailed in our recent white paper . We use the merchant qualifier because some hyperscalers have developed their own congestion-management schemes that work with standard Ethernet-switch hardware. One example is Amazon, which developed the scalable reliable datagram (SDP) protocol for use with its internally-developed Ni...

To train the latest AI models, cloud-service providers are investing in large accelerated-compute clusters. AI  training, however, presents different requirements for network architects than standard compute instances.  Proprietary interconnects have dominated these clusters as the most-performant solutions. Here, we examine  an alternative fabric architecture built around ubiquitous Ethernet technology. Broadcom sponsored the creation  of this white paper, but the opinions and analysis are those of the author. Download the full  white paper  for free, no registration required.

About 18 months after acquiring Innovium, Marvell announced its next-generation Teralynx 10 data-center switch chip. The 51.2Tbps design moves the Teralynx architecture to 5nm process technology while also incorporating homegrown 112Gbps PAM4 serdes. It marks the end of the road for the 7nm Teralynx 8 chip, which Innovium sampled but was unable to move to production. Multiple sources confirm that third-party serdes IP was the culprit, and Innovium was only one of several affected customers. The end result for Marvell is that it skipped the 25.6Tbps generation and set its sights on 51.2Tbps. Meanwhile, it has shipped more than 5 million 400GbE ports with the first-generation Teralynx 7, mostly to one hyperscale customer. Teralynx 10 promises an unsurprising feature set, which actually validates Innovium's design approach. The startup found the right balance of programmability and performance, enabling protocol flexibility and P4 in-band networking telemetry (P4-INT). Innovium also t...