Marvell Teralynx Leapfrogs to 51.2T

About 18 months after acquiring Innovium, Marvell announced its next-generation Teralynx 10 data-center switch chip. The 51.2Tbps design moves the Teralynx architecture to 5nm process technology while also incorporating homegrown 112Gbps PAM4 serdes. It marks the end of the road for the 7nm Teralynx 8 chip, which Innovium sampled but was unable to move to production. Multiple sources confirm that third-party serdes IP was the culprit, and Innovium was only one of several affected customers. The end result for Marvell is that it skipped the 25.6Tbps generation and set its sights on 51.2Tbps. Meanwhile, it has shipped more than 5 million 400GbE ports with the first-generation Teralynx 7, mostly to one hyperscale customer.

Teralynx 10 promises an unsurprising feature set, which actually validates Innovium's design approach. The startup found the right balance of programmability and performance, enabling protocol flexibility and P4 in-band networking telemetry (P4-INT). Innovium also touted large packet buffers, and Teralynx 10 weighs in at greater than 200MB. The new chip is the first to handle 512x100GbE ports, twice the radix of announced competitors. The 112Gbps PAM4 serdes blocks build on Marvell's first 5nm PHY, the 88X93160, which sampled nearly two years ago. The major caveat is that Teralynx 10 has not yet reached customers: samples are due in 2Q23.

An announcement in the absence of samples is a good excuse to revisit the checkered history of competitors attempting to unseat Broadcom. The figure below shows the companies still in the running, which eliminates Intel, MediaTek, and Xsight Labs. Although Cisco has yet to announce its 51.2Tbps switch, it deserves recognition as the only vendor aside from Broadcom to have delivered a 25.6Tbps chip. Nvidia chose to skip the 25.6Tbps generation, likely in an attempt to catch up with Broadcom. It has yet to announce Spectrum-4 availability, however, suggesting the chip's schedule may have slipped.

400/800G Ethernet Switch Roadmap

Unfortunately for Marvell, we expect Broadcom will release Tomahawk5 to production by the time Teralynx 10 samples. This partially explains Marvell's positioning of its chip for 1U designs using 32x1.6T OSFP-XD modules, forgoing the 2U 64x800G systems representing the first 51.2Tbps designs. Another factor is the company's leading position in PAM4 DSP chips used in optical modules, by way of its Inphi acquisition. Although pluggable modules are decoupled from switch chips, components for the former give Marvell access to hyperscale customers, opening the door for Teralynx. With more than four years between Teralynx generations, the company must now execute flawlessly as it works to recoup its $1 billion investment. 

UPDATE March 15, 2023: As expected, Broadcom announced Tomahawk5 production.

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